Currently, many applications are related to complex big data computing such as fingerprint recognition and machine learning. For current big data computing, performance bottlenecks of a computing system mainly lie in the following two aspects:
Memory wall: With development of technologies, processor performance is continuously improving. However, memory performance improves quite slowly. Consequently, memory performance becomes a “short slab” for improving overall system performance, and this is referred to as a memory wall. Specifically, connection and communication between a processor and a memory are implemented by using an input/output (I/O) bus. Limited by hardware, the I/O bus has limited bandwidth. Consequently, in most time, the processor is in an idle state of waiting for memory.
Power wall: Currently, most memories are volatile memories. Therefore, to prevent a data loss, the volatile memories need to be energized all along. This leads to high dynamic power consumption and high static power consumption of the memories.
Generally, the following solutions are provided to the foregoing two problems.
A solution to the memory wall: A logic unit (or logic circuit) may be added to a memory, so that data is directly computed in the memory, that is, in-memory computing. Using summation of 10 numbers as an example, if the memory has only a data storage function, the processor needs to read the 10 numbers from the memory through an I/O bus, and sum the 10 numbers. If the memory has a logic operation function, the memory can directly compute the sum of the 10 numbers, and then send a computing result to the processor through the I/O bus. It may be found, from a comparison between the foregoing two implementations, that a memory with the logic operation function reduces transmission pressure of the I/O bus by 90%, so that memory wall restriction can be effectively mitigated.
A solution to the power wall: A non-volatile memory may be used to replace the volatile memory. Because the memory is non-volatile, a loss of data in the memory caused by power interruption does not occur. Therefore, in a data processing process, the entire memory does not need to be energized all along. In this way, power consumption is effectively reduced.
Development of a resistive random access memory (RRAM) technology makes it possible to resolve the foregoing two problems at the same time. First, a core device of an RRAM is a memristor (that is, a resistor in the RRAM is a memristor). The RRAM is non-volatile and can reduce power consumption. Further, as shown in FIG. 1, the RRAM has a crossbar array structure (therefore, the RRAM is generally referred to as an RRAM crossbar array, or an RRAM crossbar). The RRAM crossbar may be single-layer or multilayer. In a multilayer RRAM crossbar, an output of a layer may be used as an input of a next layer. A resistor array is disposed at each layer of the RRAM crossbar. If the resistor in the RRAM is considered as a neuron in a neural network, it may be found that the RRAM crossbar is structurally very similar to the neural network. Such a structure is very suitable for logic operation. Specifically, various logic operations may be implemented by configuring a quantity of layers of the RRAM crossbar, a size of a resistor array at each layer of RRAM crossbar, and a resistance value of each resistor.
In the prior art, a logic operation capability of the RRAM crossbar is already developed and used to some extent. FIG. 2 shows a conventional circuit structure of an RRAM crossbar that can perform a logic operation. First, a resistance value of a resistor in the RRAM crossbar needs to be configured according to a desired logic operation function (such as summation, exclusive OR, and matrix multiplication). Using matrix multiplication Y=ΦX as an example, first, each element in a matrix Φ may be stored in the RRAM crossbar. For example, a resistor Gij in FIG. 2 corresponds to an element in the ith row and the jth column of Φ, and a resistance value of Gij represents a value of the corresponding element. Then, in actual matrix multiplication, elements of a matrix X are first converted from digital parameters x1 . . . xn into analog parameters (analog voltage signals), and are then input into rows of the RRAM. Then a point multiplication operation is performed on the elements in the matrix using voltage, current, and resistance relationships between rows and columns in the RRAM crossbar, so as to obtain computing results V1 to Vm. Finally, the computing results (analog voltage parameters) are converted into digital parameters (such as y1 and y2) and are then output.
It may be learned, from the description above, that a conventional RRAM crossbar uses an analog parameter to perform a logic operation, and such an operation manner mainly has the following two disadvantages:
First, a large quantity of digital-to-analog converters (DAC) and analog-to-digital converters (ADC) are required for DA and AD conversion operations on signals. The converters and the conversion operations are time-consuming and power-consuming.
Second, to implement specific operation logic, the resistor in the RRAM needs to be configured or programmed in advance. In practice, the resistance value of the resistor in the RRAM is determined according to an integral of a current that flows through the resistor. However, characteristics of resistor elements in the RRAM are not constant and may fluctuate to some extent. Consequently, resistance values obtained by an integral operation on a same current may be different. Specifically, as shown in (a) in FIG. 3, affected by fluctuation of element characteristics, a resistor has different state conversion curves (from an Ron state (also referred to as a low resistance state, or an on-state) to an intermediate state and then to an Roff state (also referred to as a high resistance state, or an off-state), resulting in inaccuracy of resistance programming. In addition, it may be learned, from (b) in FIG. 3, that such inaccuracy is especially apparent in the intermediate state of the resistor.